The invention relates to operational amplifiers. More specifically, the invention relates to offset error calibration in an operational amplifier.
There are many different uses for operational amplifiers. For example, operational amplifiers may be used as unity gain amplifiers and transimpedance amplifiers. They may also be used as direct injection charge amplifiers.
Offset error can be an important issue in the design of operational amplifiers. For instance, the output of a typical unity gain amplifier without offset error correction is vo=vi+ofst, where vi is the input voltage, ofst is the offset voltage and vo is the output voltage. The output of a typical direct injection charge amplifier without error offset correction is vo=v+ofst, where v is a prescribed voltage.
The source of offset error may arise from the physical design of the operational amplifier or it may arise from process variations. Circuit thresholds, the mismatch of device sizes, and circuit operating conditions are all sources of offset error. Physical size variations inherent in the process of integrated circuits and process parameter variations are sources of offset error that come from manufacturing processes and are basic limitations of the process technology. In CMOS operational amplifiers, threshold voltage process variations provide a major source of offset error.
Different analog techniques for calibrating offset error have been suggested. One analog technique involves correct transistor sizing and careful physical layout to minimize the basic offset parameters. Even with an optimal design, however, offset correction by design alone might not be good enough to hold the offset voltage to within tens of micro-volts.
Another analog technique involves the use of a switched capacitor circuit for correcting offset error. A typical switched capacitor circuit uses a high gain operational amplifier to correct for differential amplifier offsets. One disadvantage of this circuit is the use of a large offset correction capacitor to sample and hold offset correction data. The capacitor is made large to minimize leakage and decay effects. Fabrication of the large capacitor also involves special IC process steps and a considerable amount of circuit area. Also, a control requirement to hold the offset voltage to within tens of microvolts results in a very high refresh rate.
Yet another technique involves analog controlled offset calibration. Differential current modification is described as a `nulling input port circuit` in Enz and Gabor; "Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization"; Proceedings of the IEEE, Vol. 84, No 11, November, 1996, page 1597. Gm modification is described as correction with a `programmable current mirror` in Yu and Geiger, "Nonideality Consideration for High-Precision Amplifier--Analysis of Random Common Mode Rejection Ratio"; IEEE Transactions on Circuits and Systems; Vol 40, No 1; January 1993; pages 1-12. With both of these analog techniques, special analog circuitry is used to generate analog control signals. Additional circuits are used to sample and store the analog control signals. Normal circuit leakage currents result in analog control signal data being refreshed frequently. In gm modification and differential current modification, the analog control techniques are subject to the same sample and hold limitations as the switched capacitor technique.